Method and device for the transfer of data in a data loop

ABSTRACT

A method and arrangement for transmitting data in a data loop comprising at least two stations and at least one of which is an overriding master station in which a transmission frame for the data to be transmitted is generated for transmission through all successive stations. Each transmission frame is generated with a predetermined constant number of clock cycles and contains exclusively the data to be transmitted from one station to one or more others and is devoid of protocol signals, especially devoid of address signals. Each transmission frame is immediately followed by the beginning of a further identical transmission frame containing the next data to be transmitted, if any. Time slots, preferably mutually equally great time slots, in the transmission frame are permanently or temporally modifiably allocated to the individual stations for information or data transfer before entering each transmission frame into the data loop. The entry of transmission frames containing data to be transmitted is only effected after sychronization of all stations. The method and arrangement are particularly well suited for process control systems.

BACKGROUND OF THE INVENTION

The present invention broadly relates to Local Area Networks and, morespecifically, pertains to a new and improved method and arrangement fortransmitting data in a data loop having at least two successivelyarranged stations.

Generally speaking, the method of the present invention is fortransmitting data in a data loop having at least two successivelyarranged stations optionally provided with peripheral devices, at leastone of which is an overriding master station, and comprises the stepsof: generating in the overriding master station transmission frames fordata to be transmitted; the step of generating transmission framesentailing generating transmission frames which are partitioned into timeslots, preferably equally great time slots, and with a predeterminedconstant number of clock cycles; and this step of generatingtransmission frames also entailing generating transmission frames forcontaining successive data to be transmitted in mutually immediatesuccession such that the termination of each transmission frame of thetransmission frames is followed by the beginning of a subsequenttransmission frame of the transmission frames.

The arrangement of the present invention is for transmitting data in adata loop wherein the data loop comprises at least two stationsinterconnected by a data transmission medium, such as cables,transmitter devices, optical conductors, electrolytes or the like,forming a closed loop, at least one station of the at least two stationsbeing an overriding master station, the overriding master stationcomprising a generator for generating transmission frames, the at leastone overriding master station comprising a transmitter device forentering the transmission frames into the data loop or into the mediuminterconnecting the at least two stations; the data transmission mediumconducting the transmission frames through all stations and back to theoverriding master station; each station of the at least two stations,inclusive of the at least one overriding master station, comprising areceiver device for the transmission frames, a synchronization deviceand at least one input-output device or input-output device port; eachstation being associated with at least one peripheral device; eachinput-output device or input-output device port serving selectivelyeither for transferring data being transmitted and contained in apredetermined data-receive position in each transmission frame to theperipheral device or for inputting data to be transferred from theperipheral device into a predetermined data-transmit position in eachtransmission frame; the data loop defining a direction of datatransmission; and each station comprising a transmitter unit arrangedsubsequent to the input-output device or input-output device port in thedirection of data transmission for transferring or entering transmissionframes into the data transmission medium, possibly with the data to betransmitted in altered form.

Data networks normally have the form of "point to point" connectionsbetween nodes or points of intersection or, alternatively, the form ofseveral stations, only one of which is permitted to transmit at onetime, are simultaneously connected to one common data transmissionmedium (cable, radio.) Information is normally serialized andtransferred or transmitted in blocks or packets. Communication betweenstations is always regulated by a network-specific protocol or set ofprocedural rules. Such protocols are, for instance, X.25 of the CCITT,Ethernet, ISO-P 802 and the like.

With the exception of time-segmented or multiplexed connections orcircuits, the transmission of data requires the control of networkaccess or priority arbitration, which calls for a certain expenditure oftime and is done on the basis of addresses and arbitration prioritycodes contained in the transmission framing. This, for instance, is alsothe case in the German Patent Publication No. 2,612,311 which describesa comparable device.

Each transfer unit or each transmission frame (information block or datapacket) requires a synchronization operation whose time overhead isfully integrated into the transmission time.

All protocols transmitted contain parity-checking or redundancy-checkingmechanism (for instance Cyclic Redundancy Checking or LRC, VRC) fordetecting transmission errors. Upon detection of transmission errors,information blocks are repeated.

Due to fluctuating network loads and consequently different arbitrationrates as well as to possible repetitions for correcting transmissionerrors, unpredictable transmission delays are caused in all known LocalArea Networks. As a consequence, these Local Area Networks or LAN'scannot be used in time-critical real time applications and control loopsor circuits.

The development or evolution of data processing installations intolocally distributed systems with central data banks and the necessity tocommunicate with distant peripheral equipment even some years ago gaverise to nearly hopeless cabling problems. The often required flexibilitycould not satisfactorily be assured by the technique of individualcabling.

Based on the typical structure and distribution of data processingunits, the following requirements are imposed on a data network:

(a) standard interfaces (e.g. V24 asynchronous) are to be provided onthe equipment interconnections;

(b) each physical connection in the data network is to be connectable toany other connection with a minimum of manipulation. The highflexibility and easy configurability required for this are to beachieved by implementation of permanent or dedicated lines, on the onehand, while the implementation of temporary connections withoutinterruption of network operation should be possible, on the other hand.

Control of the connection circuit or routine should be possible eitherby means of a central routing processor or by intelligent equipmentinterfaces or manually from each station (routing units).

(c) Many available data or communication channels of medium data rate aswell as high speed data or communication channels should beimplementable at freely selectable data rates on the equipmentinterfaces.

(d) Protocol transparency is desirable, which means that each end to endlog should be implementable in the data loop, the data loop shouldbehave like a physical connection (no store and forward operation) andmoreover, the system should be absolutely insensitive to transmissioncontrol characters.

(e) High reliability and low residual error rate by use of an opticalmedium (galvanic decoupling between the individual loop stations), errordetection, error localization and diagnosis up to the equipmentinterface as well as central documentation of all errors and operationalfailures should be possible.

SUMMARY OF THE INVENTION

Therefore, with the foregoing in mind, it is a primary object of thepresent invention to provide a new and improved method and apparatus fortransmitting data in a data loop which does not exhibit theaforementioned drawbacks and shortcomings of the prior artconstructions.

Another and more specific object of the present invention aims atproviding a new and improved method and arrangement of the previouslymentioned type for transmitting data in a data loop in whichre-synchronization at each transmission is omitted and there is only asynchronization check.

Yet a further significant object of the present invention aims atproviding a new and improved arrangement of the character describedwhich is relatively simple in construction and design, extremelyeconomical to manufacture, highly reliable in operation, not readilysubject to breakdown or malfunction and requires a minimum ofmaintenance and servicing.

Now in order to implement these and still further objects of theinvention which will become more readily apparent as the descriptionproceeds, the method of the present invention is manifested by thefeatures that: the step of generating transmission frame entailsgenerating transmission frames which exclusively contain data to betransmitted from a first station of the two successively arrangedstations to at least one further station of the two successivelyarranged stations and which are devoid of protocol signals, inparticular devoid of address signals, selectively permanently ortemporally modifiably allocating each time slot of the time slots intowhich the transmission frames are partitioned to at least onepredetermined station of the two successively arranged stations for datatransfer, synchronizing all stations of the at least two successivelyarranged stations to one another; subsequently entering the transmissionframes into the data loop in immediate succession; and transmitting thetransmission frames through all stations successively.

The arrangement of the present invention is manifested by the featuresthat: the generator is constructed to generate the transmission frame inimmediate succession with a predetermined constant number of clockcycles and devoid of protocol signals, in particular devoid of addresssignals; the transitter unit being arranged and constructed to enter thetransmission frames into the data transmission medium in immediatesuccession; a respective routing unit being associated with eachinput-output device or input-output device port; the transmission framescomprising predetermined time slots; the routing unit serving forallocating at least one of the predetermined time slots to each stationof the at least two stations inclusive of the overriding master station,for transferring the data to be transmitted; the overriding masterstation comprising a synchronization identifier detection device fordetecting the synchronization of all stations of the at least twostations; and the synchronization identifier detection device alsoserving for initiating entry of data transmission frames of saidtransmission frames which contain data to be transmitted into the datatransmission medium.

An advantage of the present invention is that real time transfer ofsignals is possible because the transmission frame is continuouslyrepeated and passed on. All codes which transmit timing or clock signalsand data simultaneously can be used; there are no arbitration problemsand transmission times are short and constant. Overhead caused by thenormally necessary transmission of sender and receiver or talker andlistener addresses in addition to the information or data to betransmitted is eliminated.

The invention will be better understood and objects other than those setforth above will become apparent when consideration is given to thefollowing detailed description thereof. Such description makes referenceto the annexed drawings wherein throughout the various figures of thedrawings there have been generally used the same reference characters todenote the same or analogus components and wherein:

FIG. 1 shows a basic arrangement for information tranfer in a data loopwith a master station and a number of secondary stations;

FIG. 2 shows a transmission frame;

FIG. 3 shows a basic circuit diagram of a master station; and

FIG. 4 shows a basic circuit diagram of a station.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Describing now the drawings, it is to be understood that to simplify theshowing thereof, only enough of the structure of the arrangement fortransmitting data in a data loop has been illustrated therein as isneeded to enable one skilled in the art to readily understand theunderlying principles and concepts of this invention. Turning nowspecifically to FIG. 1 of the drawings, the arrangement illustratedtherein by way of example and not limitation and employed to realize themethod as hereinbefore described will be seen to comprise stations 1,2 .. . n forming a data loop 100 in which information is transmittedbetween individual station 1,2 . . . n and an overriding or continuousmaster station 3 via a transmission medium 5. At least one masterstation 3 and one further station 1,2 . . . n are necessary for formingthe data loop 100. The number of stations 1,2 . . . n, of which at leastone must be a master station 3, is not limited. The master station 3initializes the data loop 100, monitors data transfer and can, if nototherwise provided for, control data transfer between the individualstations 1,2 . . . n and between itself and the stations 1,2 . . . n.Each of the stations 1,2 . . . n can receive data to be transferred viaport modules (I/O ports 19 from peripheral devices 4 of any given form(processors, auxiliary devices, controllers and the like) and cantransmit to any given other peripheral device 4 at the same or any otherstation 1,2 . . . n. The data or information is input by the device 4 tothe station 1,2 . . . n, the station 1,2 . . . n transmits it via thedata loop, i.e., the medium 5 interconnecting the stations 1,2 . . . n(cable, optical conductor, transmitter devices, electrolyte or the like)to other stations 1,2 . . . n or to itself or to other devices 4connected to it; the information is output by the appropriate associateddevices 4 of the receiving stations 1,2 . . . n. The allocation of themutually communicating devices 4 can be fixedly predetermined (by meansof hardware) or temporarily established (for instance by appropriateinstruction input or routing units). However, allocation is alwaysdetermined prior to data transmission, so that the transmission framedoes not have to contain any addresses or protocol signals. Compared toother configurations (such as, for instance, star configurations), theloop structure yields the shortest cabling lengths for station linkage.A further advantage of the loop structure resides in the easyexpandability of the configuration by the insertion of further stations.

FIG. 2 shows the format of a transmission frame or information blocktransmitted between the stations 1,2 . . . n in the data loop. Theframe, which may be of any given length, in the instant case shows 512time slots or sectors 28 of identical length which are consecutivelynumbered from 0 to 511. In the instant, exemplary case, the first timeslot 28 with the number 0 shows a transmission frame with an imprintedor imposed signal consisting of a number of bits or check bits whichmake transmission errors detectable due to their particularconfiguration. The check bits are arranged in such a manner that anadvance or lagging of the signal in comparison to an identical sampleavailable in the stations can be determined, in particular an advance orretard of up to two cycles, i.e. a signal shift can be detected ascycle-shifted by comparison with the sample in a flag detector. A numberof further bits (status bits), or the same bits with changed signalcontent, in this exemplary case also arranged in the time slot 28 No. 0,is used for transmitting information for identifying the status of thedata loop or for establishing or transmitting certain functions in thedata loop, such as, for instance, a synchronization of the data loop atransfer of the data transfer or Read/Write signal and data enable pulserelease from or in time slots 28 of the transmission frame carrying dataor information. Depending upon the type of signal and the status bits,employment will be made in the following of the terms synchronizationidentifier, transfer flag identifier and error identifier. Theseidentifiers or "MARKS" do not have to be positioned at the beginning ofthe transmission frame and can be longer than one time slot 28. Dataimprinted in any freely selectable spot or position within the frame cangive the signal "loop complete" or "data enable" and can, in conjunctionwith further data constitute an identifier. It is of advantage, however,to impress or impose such identifiers at the beginning of thetransmission frame.

The information is transmitted in the data loop in a time multiplexprocess or procedure with fixed frame format. The data rate in anoptical conductor, for instance, is 6144 Mbits/s. The transmission frameshown in FIG. 2, for instance, consists of 512 time slots 28 of a widthof e.g. 10 bits each, with the maximum transmission time for a10-bit-word approximately corresponding to the circulation time of aframe through the data loop and back to the transmitting station (about1 ms). The transmission frames are transmitted without interruption,which means that the 511th time slot 28 of the last transmission frameinput into the loop is immediately followed by the zeroth time 28 of thefollowing identically formatted frame.

A bi-phase code is preferred for coding the transmission frame data.This simplifies recovery of the bit timing or clock and improves errorcontrol. It is noted that at the start of operation, or after errordetection, a pure synchronization transmission frame simply containingthe synchronization identifier without any further user information ordata is transmitted.

Of the 512 time slots 28 contained in the transmission frame, eighteenare used in the instant exemplary embodiment for control and monitoringof the loop, i.e. for handshaking. A time slot 28 contains thesynchronization identifier or mark for initial loop synchronization orthe transmission flag for enabling the loop for data input or output andthe simultaneous synchronization check. Two time slots 28 are used forhardware signals and 15 fifteen time slots 28 are used for loopadministration and connection and disconnection between the stations 1,2. . . mn, but not for allocation of the data contained in the sametransmission frame to specific stations 1,2 . . . n or devices 4.

Due to the structure of the data loop, each one of the remaining timeslots 28 of the transmission frame is suitable for servicing abidirectional and full duplex channel due to the structure of the loopwith a maximum data rate of 9600 bits/s.

It is noted that the transmission frame as such can be of nearly anydesired length and that it can be subdivided into integral numbers oftime slots 28 of any desired size, i.e. duration. Unused time slots 28can be kept in reserve for larger volumes of data traffic.

As shown in FIG. 3, the master station 3 is provided with a permanentlyrunning clock generator 21 which supplies all the timing signalsrequired for the system and feeds these via a conductor a to a frameformat counter 22, a central control unit 24, to a data shaft registerunit 6 and to an encoder 7. The frame format counter 22 connected to theclock generator 21 subdivides or partitions a predetermined transmissionframe (FIG. 2) into individual time slots 28 containing individual databits and determines the time of the output or generation of asynchronization identifier or of a transmission flag in one or more timeslots 28 in the central control unit 24 via a conductor b. The currenttime slot number at transmission of the frame appears at an output c ofthe frame format counter 22 and is fed to a flag generator 23 as well asto a time delay memory or intermediate buffer memory 18.

The flag generator 23, at appropriate times predetermined by the centralcontrol unit 24 via a conductor e, supplies at an output d thesynchronization identifier or mark or the transmission flag, oralternatively, an error identifier or mark depending on the momentarystatus of the data loop, preferably at the beginning of transmission ofthe frame or at the cycle time for the zeroth time slot 28; thisinformation is transmitted to a port control logic unit 25 connected tothe central control unit 24 and the buffer memory 18. At start oftransmission operation, the synchronization identifier is transmitted bythe flag generator 23.

The central control unit 24 controls data transfer in the port controllogic unit 25 via an output h and operations in the data shift registerunit 6 via a conductor or line f as a function of the operational statusof the data loop, which information arrives via a conductor g from anerror and control logic unit 12. The status bit(s) in the identifier is(are) modified or set, or the synchronization identifier is transformedinto a transmission flag (data transmission enable), via a conductor e.

The master I/O port control logic unit 25, as a function of signalsreceived via a conductor h, presents the signals arriving via aconductor j of the time delay memory or buffer memory 18 or the data ofthe flag generator 23 arriving via a conductor d to the data shaftregister unit 6 as output data via a conductor i.

The data received in the data shift register unit 6 in parallel form viaa conductor i are transformed into serial information or data with theaid of a control signal received from the central control unit 24 viathe conductor f and the cycle or clock signal received from the clockgenerator 21 via the conductor a and transmitted to the encoder 7 via ka conductor.

The encoder 7 combines the data information arriving via k the conductorand the cycle or clock signal arriving via a to the conductor aself-clocking clock-data signal which is transmitted via a conductor 1to a transmitter device or transmission register 8 in which the codedclock-data-signal is brought into a form suitable for the datatransmission medium 5, for instance an optical conductor, e.g. as lightpulses.

Via the data transmission medium 5, the generated transmission frame isconsecutively transmitted to the successive stations 1,2 . . . n andreturns to the overriding master station 3 which is provided with amedium interface or receiver device 9 for incoming transmission frames.The signal coming from the data transmission medium 5 is transformedinto an electronic clock-data signal the in the self-clocking code andis transmitted via a conductor o to a decoder 10. Missing frames,missing synchronization identifiers or missing transmission flags whichare otherwise expected are reported to the error and control logic unit12 via a conductor t.

In the decoder 10, the received clock-data signal is separated into aclock signal and data signals. The clock signal is transmitted via q aconductor to a frame format counter 13, the error and control unit 12and a shift register 11. The data signals are transmitted to the shiftregister 11 via a conductor p. Absence of the clock-data-signal isreported to the error and control logic unit 12.

The serially received data information is controlled via the conductor pby the clock signal transmitted via the conductor q and the controlsignal transmitted by the error and control logic unit 12 via aconductor r to enter the shift register 11 and be presented at the bussu as received data in parallel form.

The output of the shift register 11 to the buss u is connected to atransmission flag detector 14 and the I/O controller or input-outputdevice 16.

The transmission flag detector 14 checks, by comparison withpredetermined patterns, the data present at the output to the buss u forthe appearance of the bit pattern of a synchronization identifier ortransmission flag or error identifier and reports, via a flag statusline or conductor y, the appearance of such a sequence of characters andthe therein encoded loop status to the error and control logic unit 12.The status indicates whether the data loop has been interrupted (erroridentifier or mark) or a synchronous data transport has taken place(transmission flag) or the loop has been synchronized (synchronizationidentifier or mark).

The error and control logic unit 12 distinguishes between threeoperational cases:

Operational case (a): data loop not synchronized; The error and controllogic unit 12 monitors, at the start transmission of operation or aftera data loop interruption, the status signal at the conductor x in orderto determine whether a valid synchronization identifier has beendetected. If a valid synchronization identifier is detected (bycomparison), a reset signal is generated and transmitted via theconductor v to the frame format counter 13. The frame format counter 13is then synchronized to the cycle of the frame received and also checksthe appropriate arrival timing of further identifiers or loop statussignals and in each case reports via the conductor w to the error andcontrol logic unit 12 corresponding information as to the clock timingof an expected loop status signal. If, however, the loop status signalreports that the data loop has been interrupted, operational case (c)applies. Otherwise, the status signal "loop complete" is generated inthe error and control logic unit 12 and transmitted to the centralcontrol unit 24 and operational case (b) applies.

Operational case (b): Data loop reported as complete according tosynchronization identifier (start of data transmission in the loop).

The error and control logic unit 12 checks if the transmission flagalways arrives at the expected time. For this purpose, the outputconductor w of the frame format counter 13 checking the frame clocksignal is polled. As long as the status signal at the conductor xindicates that the ring is in synchronism and no other error report (t,s) is made to the error and control logic unit 12, an enable signal viathe conductor gg permits data transfer through the I/O controller oninput-output device 16 and data transfer from the port modules or I/Oports 19 to the peripheral devices 4.

On occurrence of an error (no reception, missing clock signal, notransmission flag at the expected time), data transfer via the conductorgg is interrupted and operational case (a) applies.

Operational case (c): Loop interrupted.

A check is made via the conductor w to determine whether a transmissionflag arrives at the expected time.

As long as the status signal present at the conductor x indicates "loopinterrupted", operational case (c) applies.

On the occurrence in the station itself of one of the errors mentioned,operational case (a) applies.

A status signal loop complete at the conductor x makes operational case(b) applicable.

The error and control logic unit 12 controls data transmission ortransfer into the buffer memory 18.

The frame format counter 13 connected to the error and control logicunit 12 and to a routing unit 15 supplies information at data outputconductor z concerning the number or position of the actually incomingor arriving time slots 28.

The routing unit 15 contains and administers the information as to whomay exchange data with whom and on which slot of the transmission frameand, at the appropriate time derived from the frame format counter 13via the conductor z, supplies the I/O controller or input-output device16 with this information via a conductor aa and enables inhibits or datainput to or extraction from the current slot.

Information from the routing unit 15 to the I/O controller orinput-output device 16 of the stations 1,2 . . . n or master station 3is either transmitted via separate control lines or is input into thetransmission frame as data to be transmitted. Inputting, however, iseffected in such a way that data input into a transmission frame forcontrolling data extraction are valid at the earliest for datatransferred in the following transmission frame. The I/O controller orinput-output device 16 controls data transmission to an input-outputport module or I/O port 19 and to the peripheral devices 4 as a functionof the address information transmitted on a buss aa of the routing unit15 and the enable signal transmitted on the conductor gg of the errorand control logic unit 12.

After possible modification by the interface or port modules or I/Oports 19, the data are presented to the buffer memory 18 via a buss dd.

The buffer memory 18 forms a data buffer. Since the transmission time ofthe frame(s) in the data loop is always shorter than the duration ofinputting the frame(s) into the data loop, these time lags or delaysmust be compensated for, and the buffer memory 18 serves this purpose.The duration of the frame(s) to be transmitted must be greater than orat least as great as the transmission time in the data loop, since animmediate succession of the frames is otherwise not possible.

The I/O ports or port modules 19 transform the data format presented atthe conductors ee by the I/O controller or input-output device 16 into aformat which is intelligible to the peripheral equipment or devices 4connected via the conductors ff and then transmit the data to theperipheral devices 4 in case of the signal on the conductor gg beingvalid or active. It is also possible to defer or delay data output fromthe station 1,2 . . . n or from the port modules or I/O ports 19 to theperipheral devices 4 until an enable signal is received via theconductor gg or a conductor o from the error and control logic unit 12which generates this signal after it has checked and found free of errora transmission flag following the transmission frame from which theinformation was taken. It is thus possible to block or inhibit the I/Ocontroller or input-output device 16 or 26 or to defer or delay signaltransmission to the port modules or I/O ports 19.

An optionally provided routing control unit 17 can modify allocationtables contained in the routing unit 15 as to allocation of the timeslots 28 in the frame to two or more peripheral devices 4 and thus formtemporary connections (not predetermined by hardware) which can ifdesired be determined by an input unit 20 via a conductor cc.

At initiation of data transmission or when switching on the system or attermination of data transmission, the data loop is interrupted and nosignal is received at the medium interface or receiver device 9. Thisabsence is reported to the error and control logic unit 12 via theconductor t. At the same time, the clock generator 21 is running. Thisstarts the following operation:

1. The clock generator 21 starts to generate a synchronization framecontaining a certain number of clock cycles. The flag generator 23, at atime defined on the conductor b by a signal of the frame format counter22, generates a synchronization identifier which is impressed on thissynchronization frame. This synchronization identifier is followed byblank time slots 28 or by time slots 28 not carrying data; after thelast time slot 28 of the frame, a newly generated, identicaltransmission frame is either provided with the same synchronizationidentifier or with a transmission flag (if the data loop is detected ascomplete as a result of the return of a synchronization identifier sentout from the master station) and so on.

The input-output port control logic unit 25 transfers this frameinformation into the data shift register unit 6. The individual framedata are then combined or merged in the encoder 7 with the clock signalarriving via the conductor a from the clock generator 21 and fed intothe data transmission medium 5 via the medium interface or transmitterdevice or transmission register 8.

2. This synchronization transmission frame devoid of information or dataruns through the data loop and then back at the medium interface orreceiver device 9. As soon as the medium interface or receiver device 9detects pure clock data on the data transmission medium 5, the error andcontrol logic unit 12 starts the search for a synchronizationidentifier. Further, the clock signal is separated out at q theconductor and the data at the conductor p and the data are input intothe data extraction unit or shift register 11.

3. At the same time, the loop is reported complete via the conductor gand the signal on the conductor gg "enable data transfer" is generated.

The transmission flag detector 14 further reports any detectedsynchronization identifier via the conductor x to the error and controllogic unit 12.

4. The error and control logic unit 12 resets the frame format counter13, in correspondence with a time predetermined by the synchronizationidentifier, to zero or initial status. From this time on, the frameformat counter 13 transfers the identifier data or of the time slot 28positioned at the output conductor u of the data extraction unit orshift register 11 via the slot-data buss z to the routing unit 15 or tothe buffer memory 18.

5. At a predetermined reference time, the frame format counter 13 givesthe signal "flag expected" at the conductor w. If no synchronizationidentifier appears at the conductor x at this time or no synchronizationidentifier is reported as detected, the operation starts over again withoperation No. 3, as there must be an error. If an identifier appears atthe right time, but is an error identifier operation No. 4. is repeated.If a correct synchronization identifier is received or no erroridentifier is determined, the central control unit 24 is informed viathe conductor g that the loop is complete and in synchronism and datatransfer is enabled as described below under operation No. 7.

6. When the central control unit 24 detects the status signal "loopcomplete" via the conductor g, it transmits via the conductor e in thetime slot 28 with the identifiers the identifier "transmission flag" orthe status signal "enable data transfer" according to operation No. 9.

7. If data transmission in the master station 3 is required internallyto an interface or port module or I/O port 19 or to a station 1,2 . . .n and one or more time slots 28 of the transmission frame are allocatedby the routing control unit 17 for this transmission, and if asynchronization identifier was detected in the transmission flagdetector 14 and this was signalled via the conductor to the I/Ocontroller or input-output device 16, then the I/O central control unit24 can initiate a data transfer, i.e. the data present at the buss u inthe data extraction unit or shift register 11 are routed via theconductors ee to I/O ports or port modules 19 and/or from I/O ports orport modules 19 and/or data coming from I/O ports or port modules 19 arereceived, that is entered into the transmission frame.

8. The data coming from the buss u--possibly modified by operation No.7, but otherwise unmodified--are stored in the buffer memory 13 and,controlled by the central control unit 24, are transmitted at anappropriate time via the port control logic unit 25 to the datatransmitter device or transmission register unit 8 for inputting intothe data transmission medium 5.

9. After detection of the status signal "loop complete" in thesynchronization identifier, the flag generator 23 impresses in the nexttransmission frame a changed or modifier status signal in the time slot28 containing the identifiers. This time slot 28 then forms or generatesthe transmission flag which enables data transfer when received in thestations 1,2 . . . n or after return to the master station 3. Framescontaining "loop complete" status signals or transmission flags aretransferred into the medium 5 until an error is detected or an erroridentifier is received. When a transmission flag with "loopsynchronized" status has been transferred into or transmitted throughthe medium 5 and, the port received again control logic unit 25 takesover the data stored in the buffer memory 18 and transfers them to thedata shift register unit 6 in the correct slot 28 or slot by slot. Thismeans that the loop and its stations 1,2 . . . n, after an initiallypure synchronization operation entailing sending out the transmissionframe without any data to be transferred, is also closed for datatransfer starting with a transmission frame following synchronizationand containing a transmission flag.

FIG. 4 shows a block diagram of a station 1 in which structural elementsof essentially identical function to those of the master station 3 andlines transferring essentially the same signals or the same informationor outputs containing essentially the same signals are provided withidentical reference numbers.

The transmission frame arriving in a station 1,2 . . . n is transferredvia the medium interface or receiver 9 to the decoder device 10 and thedata, after separating out the clock signal, are taken via the conductorp into a data exchange or shift register 33 which is clocked by theclock signal arriving via the conductor q.

When the information of an entire time slot 28 is in the data exchangeunit or shift register 33, a transfer of the data via the conductor uand the buss y' can be effected by a control signal k of the error andcontrol logic unit 12. the conductor u constantly displays the datainformation currently present in the data exchange unit or shiftregister 33. In the buss y' of one of the input-output devices or I/Ocontrollers 26, the information newly to be transferred into the timeslot 28 of the data exchange or communication unit or shift register 33is displayed.

At the output k of the data communication unit or shift register 33, thedata frame containing possibly modified information reappears in serialform and is transferred via the encoder 7 to the input device ortransmission register 8 which in this case offers the additionalpossibility of inhibiting any output of the station 1,2 . . . n to themedium 5 by means of the signal l' in the event of system malfunction.

The error and control logic 12 receives via the conductor x a statussignal from the transmission flag detector 14 which indicates whether asynchronization identifier or a transmission flag were detected in thearriving transmission frame. If a valid identifier is detected, a signalv for resetting of the frame format counter 13 is generated.

From now on, a transmission flag is always expected in the error andcontrol logic unit 12 at the same time or clock cycle determined by asignal in the conductor w and the error and control logic unit 12 checkswhether the transmission flag is detected in the transmission flagdetector 14 at the time or clock cycle to be expected or the time orclock cycle determined by the signal in the conductor w.

If a synchronization identifier is detected, the synchronization processin the station 1,2 . . . n will start all over again.

If the synchronization flag is found to be in order or if thetransmission flag status indicates "loop closed" which, a signal in theconductor o' sets "enable data transfer" in the I/O controller orinput-output device 26, which permits initiation of data transfer.

In the event of an error arising in the station 1,2 . . . n itself,(missing clock signal, hardware error or the like), access to the medium5 by the medium interface or transmission register 8 is prevented by theconductor l' of the medium interface 8.

In the event of non-receipt of a transmission frame, an "error frame"with an error identifier is generated via a signal in the conductor n inthe flag generator 23 which receives the frame information and time slotdata via the conductor z. The error identifier contains data concerningthe failure or the station and is transmitted via the I/O controller orinput-output device 26 and the buss y' or the data communication unit orshift register 33 to the medium 5 and via all the stations 1,2 . . . nto the master station 3.

Depending upon the enable signal in the conductor o' and the addresssignal in the buss aa of the routing unit 15, which indicates whether anI/O port 19 or which interface module or I/O port 19 is allocated forthe actually arriving time slot 28 for data transfer, the available timeslot data are transferred from the buss u to the port control logic orI/O controller 26 and presented by the latter via the conductor y' tothe data communication unit or shift register 33 as output data with orwithout modification of the data by the port modules or I/O ports 19.

At initiation of operation, there is no reception in the station 1,2 . .. n. At this starting point, the frame format counter 13 runs freely,driven by an internal clock signal.

The error and control logic unit 12 detects via the conductor t thatthere is no reception at the medium interface or receiver 9 It blocks orinhibits via the conductor o' data transfer in the I/O controller orinput-output device 26 and in the port modules or I/O ports 19 andenables via the conductor n the flag generator 23 to generate a datatransmission frame with the aid of the clock signal of the frame formatcounter 13 on which the error identifier is impressed by the flaggenerator 23 and which is transmitted to the data communication unit orshift register 33 via the I/O controller input-output device 26, isencoded in the encoder 7 and transferred via the transmission register 8to the medium 5, possibly repetitively.

As soon as the medium interface or receiver 9 detects clock signal data,these latter are separated by the decoder 10 into clock signals anddata. The medium receiver 9 reports via the conductor t "reception" tothe error and control logic unit 12. The data are now received in thedata communication unit or shift register 33 after enabling via theconductor k'.

When the transmission flag detector or comparator 14 reports asynchronization identifier via the conductor x, the frame format counter13 is reset via the conductor v.

From now on it is monitored whether a transmission flag is reported viathe conductor x at the time of expectation of transmission flagsindicated via the conductor w. If this is not the case, or if a cycleerror is reported via the conductor s, all output of the station isblocked or inhibited via the conductor l'.

If, however, "loop synchronous" is detected via the conductor x in thetimely arrived transmission flag, the I/O controller or input-outputdevice 26 receives the message "data transfer enable" via the conductoro', whereupon data can be extracted or read from or input into the timeslots 28 in the data communication unit or shift register 33, with theport modules or I/O ports 19 being allocated to the respective timeslots 28 under control of the routing unit 15.

The routing unit 15 controls data transfer by means of time slots 28allocated to the station 1,2 . . . n. If required, for instance if aconnection is to be established, a request for allocation of one or moretime slots 28 for this connection can be addressed to the routing unit15 of the master station 3 by transmission of a corresponding request inthe time slots 28 reserved for the routing system. A reply to thestation 1,2 . . . n is transmitted via the medium 5 and an optionalcorresponding change in the number of time slots 28 allocated to thestation 1,2 . . . n is made known to the routing unit 15.

The basic procedure is thus the following: For the synchronization ofthe station 1,2 . . . n or the frame format counter 13 with thetransmitted frame, in the instant case, for instance, time slot 28 Owith 10 bits is used. In this time slot 28, a particular bit pattern(synchronization identifier) is constantly transmitted. Each stationcompares an 8 bit length of this pattern with a reference bit pattern.If no coincidence occurs at the expected time, there is certainly anerror in the transmission or in the station logic.

In this case, any further data transmission to the port modules or I/Oports 19 is blocked or inhibited. Resynchronization is also effected byusing this particular time slot 28. This resynchronization following anerror is controlled by the master station 3 which releases the framesfor data transmission after resynchronization and continues to transmitresynchronization identifies until it receives one itself and thereupontransmits the "enable data transfer" flag or the transmission flag.

A connection is allocated one or more time slot(s) 28, in the case of adedicated line permanently, otherwise temporarily. In the case of adedicated line, the allocation of a channel of a station 1,2 . . . n toa time slot 28 can be effected via a not particularly shown PROM modulelocally in each station 1,2 . . . n (for instance, in order to define adedicated line between station 1 interface number 16 and station 4interface number 3, one time slot 28 (e.g. time slot 28 number 37) instation 1 must be allocated to interface number 16, while the same timeslot 28 number 37 must be allocated to interface number 3 in station 4.)

In case of a temporary connection, this allocation is established bycorrelation of the local and central routing unit 15 by a notparticularly shown relay center.

Inputting of the connection request can be done either manually via aninputting unit 20, via an intelligent interface port(protocol-controlled) or from the relay center.

The time required for establishing the connection strongly depends onthe type of connection and the desired documentation and the validitycheck. In the simplest case, a point to point connection withoutdocumentation and checking requirements, the connection can be expectedto be established within 4 to 10 ms.

The maximum transmission time for a 10 bit word (time slot 28) thuscorresponds to the circulation time of a frame through the loop. Sincethe transmission time of the frame is always constant and about 1 ms,real time transmissions can be effected with a precision of about100-200 ns. A constant transmission delay is required for closed loops.

The interfaces of the stations to the input and output devices areadvantageously conventional standard interfaces.

By using an internal "intermediate standard" (ee), it is possible toconvert the data format during transmission (for instance connectionfrom a device with serial interface to a device with 8 bit parallelinterface) without particular conversion hardware and software. This isonly possible, however, if a protocol conversion is not also required.

Examples for standard interface modules:

V 24/RS232C ASYNC: up to 19,2 kbit/s

(8 bit data+2 control signals)

20 mA current loop: up to 9,6 kbit/s

(8 bit data+2 control signals)

Intelligent interface:

This module can serve up to four V 24/RS232C interfaces at 19,2 kbit/s,buffer the data and effect protocol handshaking. It can also be adaptedto particular requirements (such as multiplexing of interfaces)

8 bit parallel I/O+two control signals

It is further possible to implement interfaces for IEEE488/IEC625 andinterfaces for the transmission of analog signals and speech. Inaddition to this, it is possible, for instance, to establish aconnection to other networks via an X.25 protocol interface unit.Moreover, when installing an additional interface in an already existingstation 1, 2 . . . n, no interruption of operation for the otherchannels is to be expected.

Due to the spatial extent of the network, particular attention was paidto reliable and rapid error identification, location and documentation.Documentation and registration of errors and operational failures ormalfunctions is effected centrally in the master station 3.

The following basic sources of errors are identified: Failure of opticalcondunctors or optical and electrical components associated with theoptical conductors, failure or malfunction of the station logic, errorsin the transmission system, errors in the interface modules.

On errors in the transmission medium, such as optical conductors thesubsequent station 1, 2 . . . n in the direction of transmissiongenerates an error message to the master station 3.

On failure of a station 1, 2 . . . n due to failure of synchronization,the respective station 1, 2 . . . n is bridged or by-passed on a circuitlevel close to the transmission line. The missing absence of thisstation is detected and reported by regular polling of the transmissionsystem.

Errors in the local part of the transmission system are detected by awatchdog circuit; the respective unit tries to transmit an error messageto the master station 3.

Errors in the interface modules can, if intelligent modules are used, bereported and logged via the transmission system. In this case, it mayalso be possible to adopt measures for the elimination of the defectiveinterface and to record diagnostic information.

Suitable transmission media are all known media such as cables(baseband, HF modulated, CATV), radio or optical transmission media, anoptical medium being preferred.

The frame contains only one transmission flag with a synchronizationcharacter which also contains information concerning status in respectof synchronization and "loop complete". The synchronization operation iseffected only once at the start of operation of the network and, ifnecessary, following a failure. During operation, synchronization isonly monitored in each station 1, 2 . . . n-once at each circulation ofthe frame. Data transmission is only enabled when perfect loopsynchronization is achieved. The transmission flag with asynchronization character controls channel allocation according to clockcycles in the time multiplexer. This has the effect that noload-dependent delay due to arbitration problems occurs and thus aconstant transmission time between two stations 1, 2 . . . n is assured.Since synchronization and data transmission are strictly separated as totime, user signals cannot disturb the synchronization. For this reason,it is possible to transmit different user protocols simultaneously onthis LAN.

It is noted that the synchronization of the stations 1, 2 . . . n andthe master station 3 in respect of one another can also be carried outexternally via separate lines. Synchronization by the circulatingtransmission frame is preferable, however. Further, there is no internalsynchronzation of the stations 1, 2 . . . n in relation to the signaljust coming in or arriving, but instead a checking as to the timelyarrival of an identifier contained in the information block or datapacket.

Detection of the incoming or arriving identifiers and their checking iscarried out in appropriate circuits, such as comparator circuits.

While there are shown and described present preferred embodiments of theinvention, it is to be distinctly understood that the invention is notlimited thereto, but may be otherwise variously embodied and practicedwithin the scope of the following claims.

Accordingly, we claim:
 1. A method for transmitting data in a data loophaving at least two successively arranged stations one of which is amaster station, comprising the steps of:sequentially generatingtransmission frames in a master station at a predetermined, constantclock frequency; partitioning each one of said transmission frames intoa predeterminate number of time slots of a predetermined duration; priorto entering data from said master station into a data loop containingsaid master station and at least one station successively arrangedthereto, generating a synchronization identifier at said master stationand occupying a preselected time slot by said synchronization identifierin a thus defined synchronization transmission frame; entering saidsynchronization transmission frame into said data loop and circulatingsaid synchronization transmission frame from said master stationsuccessively through said at least one station and said data loop backto said master station in order to synchronize said master station andsaid at least one station; signalling synchronization of the at leastone station to said master station and selectively repeating said stepof circulating said synchronization transmission frame through said dataloop until the at least one station is synchronized with said masterstation; generating a transmission flag and a synchronization flag atthe master station and occupying, in a data transmission frameimmediately following said synchronization transmission frame, apreselected time slot by said transmission flag, a preselected time slotby the synchronization flag and further time slots by data associatedwith said at least one station of said data loop; after establishingsynchronization, entering said data transmission frame immediatelysequentially to said synchronization transmission frame into said dataloop and continuously circulating said data transmission framesuccessively through said at least one station of said data loop back tosaid master station; during said step of continuously circulating saiddata transmission frame through said at least one station, identifyingsaid synchronization flag and said transmission flag at said at leastone station and, after identification, substantially immediately andwithout intermediate storage communicating data between said at leastone station and said data frame transmission time slots associated withsaid at least one station; selectively generating a transmission flag insaid at least one station and entering said transmission flag conjointlywith data to be transmitted from said at least one station intopreselected time slots of said data transmission frame; said step ofentering said data transmission frame into said data loop entailingentering said data transmission frame into said data loop for apredeterminate input time period; said step of continuously circulatingsaid data transmission frame entailing circulating said datatransmission frame through said data loop during a circulation periodsmaller than said input time period; and buffering said data of saidcontinuously circulating data transmission frame on return to saidmaster station prior to continuing said step of continuously circulatingsaid data transmission frame.
 2. The method as defined in claim 1,further including the steps of:providing at least one peripheral deviceat said at least two successively arranged stations; and said step ofimmediately communicating data between said at least one station andsaid associated time slots of said data transmission frame includingdata communication with said at least one peripheral device.
 3. Themethod as defined in claim 2, wherein:said step of communicating databetween said at least one station and said time slots associated withsaid at least one station entails extracting data from said associatedtime slot of said data transmission frame and transferring saidextracted data to said at least one peripheral device.
 4. The method asdefined in claim 3, further including the step of:additionally to thestep of extracting data from said time slot associated with said atleast one station and transferring said extracted data to said at leastone peripheral device, inputting data to be transmitted from said atleast one peripheral device to an other one of said at least twosuccessively arranged stations into the time slot of said datatransmission frame associated with said other station.
 5. The method asdefined in claim 2, wherein:said step of communicating data between saidat least one station and said time slots associated with said at leastone station entails inputting data to be transmitted from said at leastone peripheral device to an other one of said at least two successivelyarranged stations into the time slot of said data transmission frameassociated with said other station.
 6. The method as defined in claim 1,wherein:said step of partitioning said transmission frames into saidtime slots entails partitioning said transmission frames into time slotsof substantially equal duration.
 7. The method as defined in claim 18,wherein:said step of sequentially generating said transmission framesentails generating transmission frames which are devoid of protocolsignals including address signals.
 8. The method as defined in claim 1,wherein:selecting as said preselected time slot occupied by saidsynchronization identifier, a first time slot located at the beginningof said synchronization transmission frame.
 9. The method as defined inclaim 1, further including the steps of:detecting a transmission errorin said data loop at one of said at least two successively arrangedstations; interrupting said step of continuously circulating said atleast one data transmission frame through the data loop in response todetecting said transmission error; generating at said one station atwhich said error was detected, an error transmission frame having apredetermined number of time slots and occupying at least one of saidtime slots by an error identifier; entering said error transmissionframe into said data loop and passing said error transmission framethrough said at least one station in said date loop to said masterstation; after receiving said error transmission frame at said masterstation, repeating said steps of generating and circulating saidsynchronization transmission frame; and after re-synchronizing said onestation, at which said error was detected, eliminating said interruptionand continuing said step of continuously circulating said datatransmission frame.
 10. The method as defined in claim 9, wherein:saidstep of detecting said transmission in said data loop at one of said atleast two successively arranged stations includes selectively detectingas said transmission error, incorrect transmission of said datatransmission frame, operational failure of said one station, omission ofdata, deficient transmission flag, incorrect occurrence of saidtransmission flag, deficient synchronization flag, incorrect occurrenceof synchronization flag.
 11. The method as defined in claim 9, furtherincluding the steps of:providing at least one peripheral device at saidat least two successively arranged stations; said step of immediatelycommunicating data between said at least one station and said associatedtime slots of said data transmission frame including data communicationwith said at least one peripheral device; during said step ofinterrupting said step of continuously circulating said at least onedata transmission frame, deferring transfer of said data from said onestation to said at least one peripheral device; receiving at said onestation a next-following data transmission frame; and after said step ofidentifying the transmission flag of said next following datatransmission frame resuming said deferred transfer of said data fromsaid one station to said at least one peripheral device.
 12. The methodas defined in claim 1, wherein:said step of generating said transmissionflag entails generating a transmission flag differing from saidsynchronization flag; and said step of identifying said transmissionflag and said synchronization flag at said at least one stationentailing the steps of comparing the time of occurrence of the relatedtime slots in relation to said synchronization transmission framepreviously transmitted and a pattern of the transmission flag and thesynchronization flag with related predetermined patterns.
 13. The methodas defined in claim 1, wherein:said step of occupying said preselectedtime slot of said data transmission frame by said transmission flagentails selecting as said preselected time slot a time slot located in astarting section of said data transmission frame.
 14. The method asdefined in claim 13, wherein:said step of selecting said preselectedtime slot entails selecting a first time slot located at the beginningof said data transmission frame.
 15. The method as defined in claim 13,wherein:said step of selecting said preselected time slot to be occupiedby said transmission flag, entails selecting as said preselected timeslot to be occupied by said transmission flag, a time slot correspondingto said preselected time slot occupied by said synchronizationidentifier in said synchronization transmission frame.
 16. The method asdefined in claim 1, wherein:said step of occupying said preselected timeslot of said data transmission frame entails selecting as said timeslot, a time slot corresponding to said preselected time slot of saidsynchronization transmission frame.
 17. An arrangement for transmittingdata, comprising:at least two successively arranged stationsinterconnected by a data transmission medium in a closed data loop; saidat least two successively arranged stations comprising a master stationand at least one station; said master station containing:means forsequentially generating transmission frames partitioned into apredeterminate number of time slots of a predetermined duration; a flaggenerator; a transmitter device operatively connected to saidtransmission frame generating means, said flag generator and said dataloop; a central control unit operatively connecting said transmissionframe generating means and said flag generator with said transmitterdevice; a receiver device connected to said data loop; synchronizingmeans connected to said receiver device; an error and control logiccircuit operatively connected with said synchronizing means, saidreceiver device and said central control unit; a routing unit connectedto said synchronizing means; an input-output device operativelyconnected with said receiver device, said error and logic controlcircuit and said routing unit; a buffer storage device operativelyinterconnected between said input-output device and said transmitterdevice and connected with said synchronizing means and said error andcontrol logic circuit; said at least one station containing: atransmitter device connected to said data loop; a receiver deviceconnected to said data loop; synchronizing means connected to saidreceiver device; an error and control logic circuit operativelyconnected with said synchronizing means and said receiver device; arouting unit connected to said synchronizing means; a flag generatoroperatively connected with said synchronizing means; an input-outputdevice operatively connected with said receiver device, said error andcontrol logic circuit and said routing unit as well as said transmitterdevice and said flag generator; each one of said at least twosuccessively arranged stations containing at least one peripheral deviceconnected to said input-output device; said flag generator of saidmaster station, prior to entering data into said data loop, generating asynchronization identifier and said transmitter device entering intosaid data loop a synchronization transmission frame which is circulatedthrough said data loop and returned to said master station, in order tothereby synchronize said at least one station and said master station bysaid synchronizing means and generate a synchronization signal; saidcentral control unit of said master station, upon receiving saidsynchronization signal, controlling said flag generator, said bufferstorage means and said transmitter device such that, immediatelyfollowing said synchronization transmission frame, there is entered intosaid data loop a data transmission frame containing in preselected timeslots a synchronization flag, a transmission flag and data associatedwith respective ones of said at least two successively arrangedstations, for circulation through said data loop and return to saidmaster station; said at least one station, upon receiving andidentifying said synchronization flag and said transmission flag by saidsynchronizing means, being controlled to selectively either transferdata from associated time slots of said data transmission frame to saidat least one peripheral device or input data to be transmitted from saidat least one peripheral device conjointly with a transmission flaggenerated by the associated flag generator into a predetermined timeslot of said data transmission without the interposition of any storagemeans; said transmitter device of said master station entering into saiddata transmission medium an immediate succession of said transmissionframes which are devoid of any protocol signals including addresssignals; and each one of said routing units associating predeterminedtime slots of said data transmission frame to respective ones of said atleast two successively arranged stations.
 18. The arrangement as definedin claim 17, wherein:said data transmission medium is selected from thegroup consisting of a cable, transmitting installation, an opticalconductor, and an electrolyte.
 19. The arrangement as defined in claim17, wherein:said means for sequentially generating transmission framesat said master station contain: a format frame counter connected to saidcentral control unit, said flag generator and said buffer storage means;a continually operating clock signal generator connected to said centralcontrol unit, said format frame counter and said transmitter device;said frame counter partitioning said transmission frames into saidpredeterminate number of time slots; and said central control unitactivating said flag generator upon receiving said synchronizationsignal.
 20. The arrangement as defined in claim 17, wherein:said masterstation contains a data read unit operatively connecting said bufferstorage means and said transmitter device; said continually operatingclock signal generator being connected with said data read unit; acontrol logic unit connected to said central control unit and said flaggenerator; and said control logic unit operatively interconnecting saidbuffer storage means and said data read unit.
 21. The arrangement asdefined in claim 20, wherein:said data read unit comprises a shiftregister.
 22. The arrangement as defined in claim 17, wherein:saidtransmitter device in each one of the said at least two successivelyarranged stations produces transmission frames containing clock-signalencoded data; said receiver device at each one of said at least twosuccessively arranged stations receiving said transmission framescontaining said clock-signal encoded data; said receiver device in eachone of said at least two successively arranged stations comprising adecoding device for separating a clock signal from data contained insaid received clock signal encoded data; said synchronizing means ofeach one of said at least two successively arranged stations containinga frame format counter connected to said decoder and said error andcontrol logic circuit, and a flag detector connected to said error andcontrol logic circuit and said frame format counter; a data transferunit operatively interconnecting said decoder and said input-outputdevice, and receiving said data from said decoder; said receiver devicebeing operatively connected to said frame format counter, said error andcontrol logic circuit and said data transfer unit; said flag detectorcooperating with said frame format counter for detecting a coincidenceof said transmission flag and said synchronization flag in said receiveddata with a predetermined pattern and their occurrence in predeterminatetime slots of said received data transmission frame; and said error andcontrol logic circuit upon said coincidence of patterns and occurrencein predeterminate time slots of said synchronization flag and saidtransmission flag, activating said input-output device.
 23. Thearrangement as defined in claim 1, wherein:said data transfer unitcomprises a data extraction unit.
 24. The arrangement as defined inclaim 1, wherein:said data transfer unit comprises a data exchange unit.25. The arrangement as defined in claim 22, further including:a portmodule interconnected between said input-output device and said at leastone peripheral device in each one of said at least two successivelyarranged stations.
 26. The arrangement as defined in claim 1,wherein:said frame format counter in each one of said at least twosuccessively arranged stations is reset by said synchronizationidentifier associated with said synchronization transmission frame; andsaid frame format counter being also reset by said synchronization flagof associated with said received data transmission frame andpredetermining the time of occurrence of the synchronization flag of anext-following data transmission frame.
 27. The arrangement as definedin claim 22, wherein:said frame format counter of each one of said atleast two successively arranged stations indicating a respectiveassociated time slot of said received data transmission frame to saidassociated routing unit.
 28. The arrangement as defined in claim 27,further including:a routing control unit; and said routing unit beingconnected to said routing control unit for determining time slotsassociated with respective predeterminate stations of said at least twosuccessively arranged stations for inputting data for such respectivepredeterminate stations from said input-output device associated withsaid routing unit.
 29. The arrangement as defined in claim 27, furtherincluding:a routing control unit; and said routing unit being connectedto said routing control unit for determining time slots associated withpredeterminate ones of said at least one peripheral devices connectedwith said routing unit.
 30. The arrangement as defined in claim 17,further including:a blocking signal generator contained in said errorand control logic circuit of said at least one station; said blockingsignal generator being connected to said transmitter device andgenerating a blocking signal upon the occurrence of an error in saidreceiver device and/or said synchronizing means; and said blockingsignal generator, by means of said blocking signal, blocking saidtransmitter device.
 31. The arrangement as defined in claim 30,wherein:said frame format counter in each one of said at least twosuccessively arranged stations, upon the occurrence of said error,generating an error transmission frame for transmission by theassociated transmitter device; and said error transmission framecontaining an error identifier and a transmission flag generated by theassociated flag generator.